Personal computers, workstations, graphic subsystems of displays, electronic games and other electrical devices all include memory systems for storing data. An ever-increasing demand exists for larger and faster memory systems. Attributes of memory technologies include data access time (i.e. speed), cost, reliability, size (i.e. density), and electrical power dissipation. Several memory technologies exist such as Floppy drives, hard drives, CD/DVD drives and semiconductor memories. Semiconductor memories include DRAMS, SRAMs, ROMs, PROMs, OTPs, EEPROMs, FLASH, and VRAM memories to just name a few. While microprocessor-processing power (i.e. speed) has increase significantly in keeping with Moore""s Law, the memory devices that communicate with the microprocessor have only been able to keep up with increasing density and not speed. Part of the problem with increasing the speed of memory devices is that as the density of memory cells increase within a given memory technology, capacitive delays, sense circuits and conventional memory layout organizations keep the access time improvements minimal. If the access times cannot be improved along with the density improvements made to the memory, the development of computer systems will falter. Therefore a need exists for a new memory architecture that not only increases density but data access time as well.
A cubic (3D) memory array is fabricated on a substrate having a planar surface. The cubic memory array includes a plurality of first select-lines organized in more than one plane parallel to the planar surface. A plurality of second select-lines is formed in pillars disposed orthogonal to the planer surface of the substrate. A plurality of memory cells are respectively coupled to the plurality of first and plurality of second select-lines.